The present invention relates generally to integrated circuit device screening methods, and more particularly, to a method that uses IDDQ testing to screen out defective integrated circuit devices.
Heretofore, IDDQ data have been analyzed using statistical techniques to evaluate whether integrated circuit devices are defective. Using such conventional techniques, those integrated circuit devices in a process lot that follow a normal distribution are considered good devices while those that do not are thrown out. This technique is not effective in screening out defective devices if the population is not normally distributed due to the single wafer processing characteristic of a process. Furthermore, the normally distributed population can also contain defective devices since no correlation exists between the device physics and the IDDQ specification.
This technique becomes less and less effective when the complexity of the integrated circuit devices is high. The IDDQ component derived from intrinsic device leakage (NMOS and PMOS transistors) is higher than the current derived from defects such as gate oxide leakage, polysilicon and barrier metal bridging. When the defective current is smaller than the intrinsic current, the statistical technique cannot detect the smaller current component. This leads to the situation where either defective devices are allowed to pass, thus compromising the reliability of the products, or good devices are screened out, which adds to the cost of the products.
Accordingly, it is an objective of the present invention to provide for an improved computer-implemented method that uses IDDQ testing to screen out defective integrated circuit devices.